1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device provided with two separate circuits used during write and read operations, respectively, for data transfer between bit lines and data buses.
2. Description of the Prior Art
In a semiconductor memory device, for example, a dynamic random access memory (DRAM) comprising matrixarranged memory cells, the memory cells are connected at the cross points of word lines and bit lines. Row selection of the memory cells is performed by selection of a word line. Column selection of the memory cells is performed by selection of a pair of bit lines in response to the output of a column decoder. Each bit line pair is connected to a sense amplifier. Each sense amplifier is also connected to a pair of dummy cells. In reading stored data, when one of the right-side memory cells is selected, the left-side dummy cell is selected. When one of the left-side memory cells is selected, the right-side dummy cell is selected. The selected dummy cell provides a reference potential during the read operation from the selected memory cell.
Between each bit line and one of a pair of data buses, a transfer gate is connected as a data transfer circuit. The signal read from the memory cell connected to the selected word line is transferred to the pair of bit lines, amplified by the sense amplifier, and supplied to the data buses through the transfer gates. In write operations, write data signals supplied from the data buses, which are usually in the form of complementary signals, are transferred to the bit lines through the transfer gates and one of the selected data signals is written into the write memory cell. In the last part of the read operation period in most practical DRAM'S, the bit lines are driven by a buffer circuit which is connected to the data buses to provide amplified output signals. That is, a rewrite operation is performed via the transfer gates to restore the bit line potential which was lost during the preceding part of the read operation period and which drove the data buses.
However, it is desirable to prevent the data stored in the memory cells from being destroyed, even if the read operation is stopped halfway. Interruption of a read operation should be permitted in order to facilitate the timing design of a system using the memory device. If the semiconductor memory device enters a precharge mode prior to the rewrite operation, the potential on the bit line, which has been changed due to redistribution of electric charge via the transfer gate between the bit lines and the data buses, is stored in the selected memory cell if there is an interruption. This results in possible destruction of the stored data in the memory cell.